1. Field of the Invention
The present invention relates to a semiconductor substrate, and a process for producing the semiconductor substrate. Particularly the present invention relates to a semiconductor substrate such as an SOI substrate and is useful as the base of an integrated circuit employing MOSFET, a bipolar transistor, and the like.
2. Related Background Art
Many studies have been made on silicon-on-insulator (SOI) structure for silicon type semiconductor devices and integrated circuits, because the SOI has low parasite capacitance and facilitates element separation for increased speed, power saving, high degree of integration, and cost reduction of transistors.
In the 1970s, Imai proposed the process for FIPOS (fully isolation by porous silicon) (K. Imai, Solid State Electronics 24 (1981), p.159). In this process, n-type islands are formed on a p-type substrate, and the p-type region including the area below the n-type islands is made selectivley porous, leaving the n-type regions nonporous. The porous silicon, which was discovered by Uhlir et al. in 1964 (A. Uhlir, Bell Syst. Tech. J., 35 (1956), p.333), has pores of several nanometers to several tens of nanometers in the interior of silicon crystal, like a sponge. It has extremely large surface area with a unit volume of several hundreds m.sup.2 /cm.sup.3 or more. In thermal oxidation in an oxygen-containing atmosphere, the porous silicon is oxidized not only at the surface but also in the interior by the oxygen having penetrated thereto. Therefore, the porous silicon layer can be selectively oxidized. Since the thickness of the oxide film is controlled by thickness of the porous layer rather than the time of the oxidation, the silicon oxide film can be formed on the porous silicon in a thickness of several ten times to several hundred times that formed by bulk silicon oxidation. Thus the porous region can be completely oxidized, leaving the n-type silicon islands not oxidized at all. By this process, silicon islands are formed on oxidized porous silicon to provide FIPOS. Since the volume of silicon increases when oxidized, the porous silicon has preferably a porosity, (pore volume)/(sum of remaining silicon volume and pore volume), of about 56% in order to prevent warpage of the wafer and formation of defects by the volume increase.
Later, an improvement of this process was disclosed, in which a porous silicon layer is formed on the entire surface of monocrystalline silicon, nonporous monocrystalline silicon is epitaxially grown on the porous silicon, a part of the epitaxial silicon layer is removed to bare the porous silicon, and the porous silicon is selectively oxidized to form SOI structure (H. Takei, and T. Itoh, J. Electronic Materials 12 (1983), p.973).
With the development of FIPOS as the application field of porous silicon, the method of growth of nonporous monocrystalline silicon layer was developed taking the application to FIPOS into consideration.
T. Unagami, et al. reported epitaxial growth on porous silicon (T. Unagami, and M. Seki, J. Electrochem. Soc., 125 (1978) p.1340), probably prior to the report on FIPOS process. In Unagami's process, a porous layer is formed on the surface of a p-type Si(111) wafer of resistivity of 0.004 to 0.15 .OMEGA.cm, and an epitaxial silicon layer is grown in a hydrogen atmosphere at 1170.degree. C. by employing SiCl.sub.4 as the source gas at a growth rate of 0.4 .mu.m/min. In the grown layer, no lamination defect was reported to be observed after Si etching. However, such a high-temperature treatment causes considerable coarsening of porous structure, which is not suitable for production of the FIPOS structure. Accordingly, after the disclosure of the FIPOS, investigation on the epitaxial layer formation have been concentrated on prevention of structure change of the porous silicon and to simultaneous decrease of the crystal defects in the epitaxial layer.
Takai at al. prevented the structure change of the porous silicon by forming a monocrystalline silicon layer at 750.degree. C. by plasma CVD employing SiH.sub.4 at a growth rate of 102 to 132 nm/min (H. Takai, and T. Itoh, J. Electronic Materials, 12 (1983) p.973; H. Takai, and T. Itoh, J. Appl. Phys. 60 (1986) p.223). Takai et al. reported that, in formation of epitaxial silicon layer on porous silicon by plasma CVD, the pores of the porous layer comes to be blocked with the increase of the epitaxial silicon layer, and estimated the transition layer having remaining pores to be about 150 nm.
Vescan et al. employed LPVPE (low pressure vapor phase epitaxy) (L. Vescan, G. Bomchil, A. Halimaoui, A. Perio, and R. Herino, Material Letters 7 (1988) p.94). In their method, porous silicon was formed at a porosity of 56% on a p-type Si substrate of resistivity of 0.01 .OMEGA.cm, and the pore walls were thinly oxidized at 300.degree. C. for one hour by dry oxidation (preoxidation). This oxidation was conducted for the purpose of preventing coarsening of the structure of the porous layer in the later high-temperature treatment of epitaxial growth and oxidation. Subsequently, the oxidation film only was removed by dipping in HF. The substrate was placed in a growth chamber, and was baked at an ultrahigh vacuum of 5.times.10.sup.-6 mbar, and thereon a nonporous monocrystalline silicon layer was epitaxially grown by introduction of SiH.sub.2 Cl.sub.2 at a temperature of not higher than 900.degree. C. A transition net of about 10.sup.5 /cm.sup.2 was found around the interface by observation of the sectional face by transmission electron microscopy. Defects traversing the epitaxial layer were also found.
C. Oules et al. conducted preoxidation and LPVPE by using SiH.sub.4 as the source gas in a similar manner as Vescan did (C. Oules, A. Halimaoui, J. L. Regolini, R. Herino, A. Perio, D. Benshahel, and G. Bomchil, Mater. Sci. Eng., B4 (1989) p.435; and C. Oules, A. Halimaoui, J. L. Regolini, A. Perio, and G. Bomchil, J. Electrochem. Soc. 139 (1992) p.3595). They conducted epitaxial growth at 830.degree. C. and 2 Torr by using H.sub.2 as the carrier gas and SiH.sub.4 as the source gas, at a growth rate of 0.5 .mu.m/min. The crystal defect density in the epitaxial layer on the porous silicon formed on p-type Si substrate of 0.01 .OMEGA.cm depended greatly on the porosity of the porous layer. It is shown that at the porosity of 50% or lower the defect density observed by plane TEM was at nearly the same level as that of an epitaxial layer grown under the same conditions on a bulk (nonporous) silicon wafer, but the absolute value thereof is not shown. Usually in plane TEM observation, the size of measurement region for one sample is about 100 .mu.m square. Therefore the detection limit for the defect density is considered to be about 10.sup.4 /cm.sup.2, or in more careful observation to be not less than 10.sup.3 /cm.sup.2. The remaining defects is presumed to be caused by particles caused by the structure of the apparatus. Therefore, the defect density should be further examined under cleaner environmental conditions.
The studies on the FIPOS process were actively conducted from 1970s to the first half of 1980s, but have declined with development of new processes for SOI structures because the formation of the surface silicon layer is limited to island shapes in the FIPOS process, which is not suitable for general purposes.
As described above, the epitaxial growth on porous silicon for the FIPOS process was required to be conducted at a process temperature of not higher than 900.degree. C. in order to prevent coarsening of the porous structure and not to retard the selective oxidation of the porous layer in the later step. Therefore, the epitaxial growth method has been limited to MBE and LPVPE which have not widely been used for semiconductor silicon production. Thus few investigations have been made on the epitaxial growth by a widely used CVD system in which the epitaxial growth is practiced in a hydrogen atmosphere at a pressure of about 10 to 760 Torr by feeding a source gas.
Recently noticed SOI forming techniques include SIMOX (separation by implanted oxygen), and wafer bonding technique. The SIMOX is proposed by Izumi of Nippon Telegraph and Telephone Corporation on 1978, in which oxygen ions are implanted into a silicon substrate, and the substrate is heat-treated at a temperature of higher than 1300.degree. C. to obtain buried silicon oxide film (K. Izumi, M. Doken, and H. Ariyoshi, Electron. Lett. 14 (1978) p.593). In this method the surface silicon layer thickness and the buried silicon oxide layer thickness are limited by control of the defect density and the quality of the oxide film, and the commercial products have a limited surface silicon thickness of 200 nm .+-.60 nm, and a limited buried oxide thickness of 390 nm. The uniformity of the film thickness is affected by variation of implanting energy for ion implantation. Therefore, sacrificial oxidation, epitaxial growth, or a like treatment is required to obtain a desired thickness of the film. In particular, in thin film formation, the film thickness uniformity tends to be lower. Further, in the buried oxide film, which is formed by coalescence of oxygen ions, pinholes are formed in the portion where the oxygen coalescence is insufficient. The pin holes would cause leakage, or poor dielectric strength.
On the other hand, various methods are disclosed for wafer bonding technology to obtain an SOI structure because of controllability of thicknesses of a surface silicon layer and a buried silicon oxide layer, and high crystallinity of the surface silicon layer. Nakamura et al. disclosed a bonding method in which wafers are bonded together without an adhesive layer or another interlayer (Japanese Patent Publication No. 39-17869). This method was not further investigated until Lasky, et al. reported on 1985 a method of thinning one of the bonded wafer, and the characteristics of MOS transistor formed thereon (J. B. Lasky, S. R. Stiffler, F. R. White, and J. R. Abernathey, Technical Digest of the International Electron Devices Meeting (IEEE, New York, 1985), p.684). In the Lasky's method, an n-type epitaxial silicon layer is formed on a first wafer containing a high concentration of boron. This first wafer and a second wafer having oxide film on the surface, after they are cleaned optionally, are brought into close contact, whereby the two wafers are bonded by Van der Waals force. By heat treatment, covalent bonds are formed between the two wafers to give a bonding strength sufficient for device production. Then the first wafer is etched from the non-bonded face by a mixture of hydrofluoric acid, nitric acid, and acetic acid to remove selectively the p' silicon wafer to leave only the epitaxial silicon layer unetched on the second wafer. In this Lasky's method, it is difficult to leave the epitaxial silicon layer in a uniform thickness on the entire face of the wafer since the ratio of the etching rate of p' silicon to that of the epitaxial (p- or n) silicon is low.
To solve this problem the etching is conducted twice. Onto a face of a silicon wafer of low impurity concentration as a first substrate, were laminated a p.sup.++ Si layer and a layer of low impurity concentration. This substrate is laminated on a second substrate similar to the aforementioned one. The first substrate is thinned at the non-laminated face by polishing, grinding, or a like mechanical method. Then the remaining first substrate is selectively etched with an etching solution to bare the entire face of the p.sup.++ Si layer having been buried in the first substrate. For the etching, an alkaline etching solution is employed such as ethylenediamine pyrocatechol, and KOH, whereby the selective etching occurs owing to the difference in the impurity concentration. Then the bared p.sup.++ Si layer is selectively removed by selective etching with a mixture of hydrofluoric acid, nitric acid, and acetic acid in the same manner as in the above Lasky's method to obtain the second substrate having thereon only a monocrystalline silicon layer of low impurity concentration. In such a method, selective etching is repeated two or more times to improve the overall selectivity and to improve thereby the uniformity of the surface Si layer thickness on SOI.
However, in the thin film formation by selective etching by utilizing the impurity concentration difference or the composition difference of the substrate as mentioned above, the selectivity of the etching is greatly affected by the profile of the impurity concentration in depth direction, as readily anticipated. That is, in heat treatment at a high temperature to strengthen the bonding of the wafers after lamination, the distribution of the impurity of the buried layer broadens to lower the etching selectivity and to deteriorate the uniformity of the layer thickness. Therefore, the heat treatment after the lamination must be conducted at the temperature not higher than 800.degree. C., and further the repeated etching is expected to be not satisfactorily controlled in mass production owing to low selectivity ratio in respective etching steps.
In the above methods, the selectivity of the etching is achieved by difference in impurity concentrations or in impurity compositions. Yonehara, one of the inventors of the present invention, disclosed a novel process therefor in Japanese Patent Laid-Open Application No. 5-21338 (EP Publication No. 0469630-A). The process of Yonehara for preparing a semiconductor member comprises the steps of forming a member having a nonporous monocrystalline semiconductor region on a porous monocrystalline semiconductor region, bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the nonporous monocrystalline semiconductor region, and removing the porous monocrystalline semiconductor region by etching. This process utilizes the etching selectivity between a porous monocrystalline semiconductor region and a nonporous monocrystalline semiconductor region, and is suitable for producing an SOI substrate, for example with an active silicon layer having a uniform layer thickness. By this method, a selective etching can be realized with a selectivity factor of as high as 100 thousands owing to the difference in structure of the porous silicon having a large surface area per unit volume of, for example, 200 m.sup.2 /cm.sup.3 from that of nonporous silicon.
In this process, the selectivity is so high that the uniformity of the epitaxially grown monocrystalline silicon is reflected in the thickness uniformity of the resulting SOI layer without any adverse effects from etching. Therefore, use of a commercial CVD epitaxial growth apparatus realizes the uniformity of the wafer thickness, for example, in the range of from .+-.4%, or .+-.2% or less, in an SOI-Si layer. In this process, the porous silicon which is employed in selective oxidation in FIPOS is used as the etched material. Therefore, the porosity is not limited to about 56%, but a lower porosity of about 20% is rather suitable. Since the porous silicon is not included in the final constituting material, the influences of warpage or distortion is mitigated, and the structure change of porous silicon and coarsening of the pores are acceptable provided that the etching selectivity is not impaired. Therefore, the temperature for the epitaxial growth is not limited to 900.degree. C. or lower. The process for preparing SOI structure disclosed in the aforementioned Japanese Patent Laid-Open Application No. 5-21338 is named ELTRAN by Yonehara (T. Yonehara, K. Sakaguchi, and N. Sato, Appl. Phys. Lett. 64 (1994) p.2108). In this process, the epitaxial growth of nonporous monocrystalline silicon on porous silicon is a very important step, and reportedly under certain growth conditions lamination defect density in the epitaxial silicon layer on the porous silicon can be 10.sup.3 to 10.sup.4 /cm.sup.2. In the ELTRAN process, the defects in the formed SOI wafer are mainly the lamination defects.
Sato, et al., the inventors of the present invention, conducted epitaxial growth on the porous layer for ELTRAN by CVD (chemical vapor deposition) in a hydrogen atmosphere by using SiH.sub.2 Cl.sub.2 as the source gas (N. Sato, K. Sakaguchi, K. Yamagata, Y. Fujiyama, and T. Yonehara, Proc. of the Seventh Int. Symp. on Silicon Mater. Sci. and Tech., Semiconductor Silicon (Pennington, The Electrochem. Soc. Inc., 1994) p.443). The prebaking temperature was 1040.degree. C., and the crystal growth temperature was 900 to 950.degree. C., which were higher than those in conventional FIPOS. However, the coarsening of the porous silicon layer structure was nearly completely prevented by preoxidation (400.degree. C., one hour, in OZ). They showed that the defects caused in the epitaxial layer were mainly lamination defects and, for decrease of the lamination defects, hydrogen prebaking prior to the growth in the epitaxial growth furnace is effective to decrease the number of pores on the surface of the porous silicon by four orders of magnitude (from 10.sup.11 /cm.sup.2 down to 10.sup.7 /cm.sup.2 or less). HF dipping immediately before the introduction of the substrate into the epitaxial growth furnace to decrease of the oxygen concentration in the vicinity of surface of the porous layer. By lengthening the time of HF dipping, the lamination defect density was lowered in the epitaxial silicon layer on the porous silicon to the level of 10.sup.3 -10.sup.4 /cm.sup.2, with a certain lower limit. On the other hand, it was suggested that the remaining pores on the surface of the porous silicon after the hydrogen prebaking become the seeds of the lamination defects. The growth rate was generally higher than 100 nm/min. Generally, the lamination defects are considered to possibly deteriorate the dielectric strength of the oxide layer. The rearrangement around the lamination defects increases leakage current in p-n junction to deteriorate the life time of the minority carrier, which is considered generally to be caused only when metal impurity exists in the rearrangement portion. Although many reports have been disclosed on the epitaxial growth on the aforementioned porous layer, no report is found which shows the crystal defects of less than 10.sup.3 /cm.sup.2 even by more sensitive detection by defect-revealing etching and optical microscope observation. Although the probability of appearing the lamination defects of 10.sup.3 -10.sup.4 /cm.sup.2 in a gate region of 1 .mu.m.sup.2 is as low as about 0.0001 to 0.00001, the defect density is high in comparison with a bulk silicon wafer, which can generally affect the yield of integrated circuits. Accordingly, the lamination defect density is desired to be further decreased.
For the crystal growth, epitaxial growth method by CVD is desired which employs a source material diluted with hydrogen and is capable of achieving thickness uniformity of the epitaxial silicon layer within .+-.4%, or more preferably within .+-.2%. By use of a usual commercial CVD epitaxial growth apparatus, the equipment investment can be lowered and the apparatus development cost can be reduced. The use of CVD epitaxial growth apparatus is convenient since it can readily enlarge the wafer size (6 inches to 8 inches).
On the other hand, it was shown that lengthening of the time of HF dipping just before introduction into the growth furnace is effective for decrease of the crystal defect density. However, in the HF dipping, the HF solution may penetrate locally into the deep interior of the porous silicon to remove the thin oxide film formed by preoxidation on the pore walls. This causes local coarsening of porous silicon, which retards removal of porous silicon by selective etching to leave the porous silicon in an island state. Therefore, a method has been desired which decreases crystal defects in the epitaxial silicon layer on the porous silicon in the CVD method by which a film can be formed with satisfactory layer thickness distribution by feeding a source gas diluted with hydrogen.
In the aforementioned method in which an epitaxial silicon layer is laminated on a porous silicon and the porous layer is removed by etching, any pinhole in the thin epitaxial silicon layer may cause penetration of the etching solution into the lamination interface. This may cause etching of the buried silicon oxide to form voids. In the resulting void portion, where no buried oxide film is present, failure of a device like a MOS transistor may result owing to instability of the underlying interface.